ds0026

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only 5%. Ringing can be controlled by damping the clock
driver and minimizing the line inductance.
Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since it also
slows down the rise and fall time of the clock signal. Because
the typical clock driver can be much faster than the worst
case driver, the damping resistor serves the useful function
of limiting the minimum rise and fall time. This is very impor-
tant because the faster the rise and fall times, the worse the
ringing problem becomes. The size of the damping resistor
varies because it is dependent on the details of the actual
application. It must be determined empirically. In practice a
resistance of 10&! to 20&! is usually optimum.
Limiting the inductance of the clock lines can be accom-
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plished by minimizing their length and by laying out the lines
such that the return current is closely coupled to the clock
FIGURE 4. Clock Waveforms (Voltage and Current)
lines. When minimizing the length of clock lines it is impor-
tant to minimize the distance from the clock driver output to
Because of the amount of current that the clock driver must
the furthest point being driven. Because of this, memory
supply to its capacitive load, the distribution of power to the
boards are usually designed with clock drivers in the center
clock driver must be considered. Figure 4 gives the idealized
of the memory array, rather than on one side, reducing the
voltage and current waveforms for a clock driver driving a
maximum distance by a factor of 2.
1000 pF capacitor with 20 ns rise and fall time.
Using multilayer printed circuit boards with clock lines sand-
As can be seen the current is significant. This current flows
wiched between the VDD and VSS power plains minimizes
in the VDD and VSS power lines. Any significant inductance in
the inductance of the clock lines. It also serves the function
the lines will produce large voltage transients on the power
of preventing the clocks from coupling noise into input and
supplies. A bypass capacitor, as close as possible to the
output lines. Unfortunately multilayer printed circuit boards
clock driver, is helpful in minimizing this problem. This by-
are more expensive than two sided boards. The user must
pass is most effective when connected between the VSS and
make the decision as to the necessity of multilayer boards.
VDD supplies. The size of the bypass capacitor depends on
Suffice it to say here, that reliable memory boards can be
the amount of capacitance being driven. Using a low induc-
designed using two sided printed circuit boards.
tance capacitor, such as a ceramic or silver mica, is most
effective. Another helpful technique is to run the VDD and
VSS lines, to the clock driver, adjacent to each other. This
tends to reduce the lines inductance and therefore the mag-
nitude of the voltage transients.
While discussing the clock driver, it should be pointed out
that the DS0026 is a relatively low input impedance device.
It is possible to couple current noise into the input without
seeing a significant voltage. Since the noise is difficult to
detect with an oscilloscope it is often overlooked.
www.national.com 6
DS0026
This has been a hypothetical example to emphasize that
Application Hints (Continued)
with 20V low rise/fall time transitions, parasitic elements can
Lastly, the clock lines must be considered as noise genera- not be neglected. In this example, 1 pF of parasitic capaci-
tors. Figure 5 shows a clock coupled through a parasitic tance could cause system malfunction, because a 7404
coupling capacitor, CC, to eight data input lines being driven without a pull up resistor has typically only 0.3V of noise
by a 7404. A parasitic lumped line inductance, L, is also margin in the 1 state at 25�C. Of course it is stretching
shown. Let us assume, for the sake of argument, that CC is things to assume that the inductance, L, completely isolates
1 pF and that the rise time of the clock is high enough to the clock transient from the 7404. However, it does point out
completely isolate the clock transient from the 7404 because the need to minimize inductance in input/output as well as
of the inductance, L. clock lines.
The output is current, so it is more meaningful to examine
the current that is coupled through a 1 pF parasitic capaci-
tance. The current would be:
This exceeds the total output current swing so it is obviously
significant.
Clock coupling to inputs and outputs can be minimized by
using multilayer printed circuit boards, as mentioned previ-
ously, physically isolating clock lines and/or running clock
00585320
lines at right angles to input/output lines. All of these tech-
niques tend to minimize parasitic coupling capacitance from
FIGURE 5. Clock Coupling
the clocks to the signals in question.
With a clock transition of 20V the magnitude of the voltage
In considering clock coupling it is also important to have a
generated across CL is:
detailed knowledge of the functional characteristics of the
device being used. As an example, for the MM5262, cou-
pling noise from the �2 clock to the address lines is of no
particular consequence. On the other hand the address
inputs will be sensitive to noise coupled from �1 clock.
7 www.national.com
DS0026
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number DS0026CN
NS Package Number N08E
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labeling, can be reasonably expected to result in a
significant injury to the user.
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DS0026 Dual High-Speed MOS Driver [ Pobierz całość w formacie PDF ]

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